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• #10253 Janos250 őstag Teasüti #10212

  Új Válasz 2019-01-20 20:10:44 #10253

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  Janos250

  őstag

  válasz Teasüti #10212 üzenetére

  Olvastam én, csak eddig nem volt időm rá, de most összeütöttem.

  RMT-vel hogy csinálnál mondjuk 100 Hz 50% PWM jelet?

  Így:
  Bár most látom, hogy Te 100 Hz-et kérdeztél, én meg 10 kHz-re emlékeztem. Sebaj, átírhatja, akit érdekel.

  Ha nem kell carrier, akkor ki kell kommentelni

  // 10 kHz RMT


const uint8_t GPIOnum = 15;
const uint8_t RMTchNum = 0;
const uint8_t DutyCycle = 50 ; // %
const uint32_t freq = 10000 ;

const uint32_t clockAPBbus = 80000000 ; // RMT use APB bus clock
const uint16_t highCiklNum = (uint16_t) ( clockAPBbus / freq / 100 * DutyCycle ) ;
const uint16_t lowCiklNum = (uint16_t) ( clockAPBbus / freq / 100 * (100 - DutyCycle) ) ;

const uint32_t RMTdata = ( ( (lowCiklNum) <<16) + (1<<15) + highCiklNum) ;


void setup() {
Serial.begin(115200);
delay(1000);
Serial.println("start setup");

pinMode(GPIOnum, OUTPUT);

*((volatile uint32_t *) (0x3FF44530 + GPIOnum * 4 )) = 0x57 + RMTchNum ;
*((volatile uint32_t *) (0x3FF000C0)) |= 1 << 9 ;
*((volatile uint32_t *) (0x3FF000C4)) &= (~(1 << 9)) ;
*((volatile uint32_t *) (0x3FF560F0)) |= 1 ;
*((volatile uint32_t *) (0x3FF560F0)) |= 2 ;
*((volatile uint32_t *) (0x3FF56020 + RMTchNum*8)) = 1 ;
*((volatile uint32_t *) (0x3FF56020 + RMTchNum*8)) |= (1 << 24) ;

*((volatile uint32_t *) (0x3FF560B0 + RMTchNum*8)) = ( (0x80 << 16) + 0x80) ; // carrier freq
*((volatile uint32_t *) (0x3FF56020 + RMTchNum*8)) |= (1 << 28) ; // carrier enable

*((volatile uint32_t *) (0x3FF56024 + RMTchNum*8)) = (1 << 17) ;
*((volatile uint32_t *) (0x3FF56024 + RMTchNum*8)) |= (1 << 3) ;

for (uint16_t i = 0 ; i<(64) ; i++ ){
*((volatile uint32_t *) (0x3FF56800 + RMTchNum *64 * 4 + i*4)) = RMTdata ;
};

*((volatile uint32_t *) (0x3FF56024 + RMTchNum*8)) |= 1 ;


Serial.println("end setup");
delay(500) ;

} // end setup


void loop() {


delay(1000) ;

} ; // end loop

/*

Comments:

*((volatile uint32_t *) (0x3FF44530 + GPIOnum * 4 )) = 0x57 + RMTchNum ; // GPIOnum output = RMT CH RMTchNum
// p 58 (Tech. Ref, 4.12 Register Summary)
// 0x3FF44530 = Peripheral output selection for GPIO_0 (GPIO_FUNC0_OUT_SEL_CFG_REG)
// (0x3FF44530 + GPIOnum * 4 ) = Peripheral output selection for GPIOnum
// 87 (0x57) = rmt_sig_out0 (p. 53 , 4.9 Peripheral Signal List)
// GPIO_FUNC2_OUT_SEL_CFG_REG


*((volatile uint32_t *) (0x3FF000C0)) |= 1 << 9 ; // BIT9, Remote Controller (p. 93)
// DPORT registers/DPORT_PERIP_CLK_EN_REG =1 : enables the peripheral clock (p 92.)
// PERIP_CLK_EN_REG (p. 95 , 5.4 DPort Register Summary)
// BIT9, Remote Controller
// DPORT_RMT_CLK_EN = bit 9 = 0x200

*((volatile uint32_t *) (0x3FF000C4)) &= (~(1 << 9)) ; // PERIP_RST_EN_REG reset for peripherals (p 95)
// BIT9 = DPORT_RMT_RST (RMT reset)
// DPORT registers/PERIP_RST_EN_REG = reset for peripherals
// DPORT_PERIP_RST_EN_REG = (DR_REG_DPORT_BASE + 0x0C4) = 0x3FF000C4

*((volatile uint32_t *) (0x3FF560F0)) |= 1 ; // bit 0 RMT_APB_CONF_REG 1 = Set this bit to disable apb fifo access
// RMT_APB_CONF_REG / bit 0 RMT_MEM_ACCESS_EN Set this bit to disable apb fifo access
// This bit must be 1 in order to access the RMT memory (p. 402.)

*((volatile uint32_t *) (0x3FF560F0)) |= 2 ;
// RMT_APB_CONF_REG / bit 1 RMT_MEM_TX_WRAP_EN This bit enables wraparound mode: when the transmitter of a channel
// has reached the end of its memory block, it will resume sending at the start of its memory region

// RMT_CHxCONF0_REG 15. Remote Control Peripheral/ 15.3 Register Summary (p 396, 397.):
*((volatile uint32_t *) (0x3FF56020 + RMTchNum*8)) = 1 ; // frequency divider's factor , bit7-0 (p. 396)
// freq = 80 Mhz / 1
*((volatile uint32_t *) (0x3FF56020 + RMTchNum*8)) |= (1 << 24) ; // memory blocks allocated to channel , bit27-24

*((volatile uint32_t *) (0x3FF560B0 + RMTchNum*8)) = ( (0x80 << 16) + 0x80) ; // carrier freq
*((volatile uint32_t *) (0x3FF56020 + RMTchNum*8)) |= (1 << 28) ; // carrier enable


*((volatile uint32_t *) (0x3FF56024 + RMTchNum*8)) = (1 << 17) ; // CLK = 80 Mhz
// bit 17: RMT_CHxCONF1_REG / RMT_REF_ALWAYS_ON_CHn
*((volatile uint32_t *) (0x3FF56024 + RMTchNum*8)) |= (1 << 3) ;
// bit 3 : RMT_CHxCONF1_REG / RMT_MEM_RD_RST_CHn Set this bit to reset the read-RAM address
// for channel n by accessing the transmitter


for (uint16_t i = 0 ; i<(64) ; i++ ){
*((volatile uint32_t *) (0x3FF56800 + RMTchNum *64 * 4 + i*4)) = RMTdata ;
};

*((volatile uint32_t *) (0x3FF56024 + RMTchNum*8)) |= 1 ;
// bit 0 : RMT_CHxCONF1_REG / RMT_TX_START_CHn . Set this bit to start sending data on channel n

*/

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