Új hozzászólás Aktív témák

• #5679 S_x96x_S addikt

  Új Válasz 2021-09-03 06:33:36 #5679

  Új hozzászólás

  Összes hozzászólása itt Válaszok az összes hozzászólására itt Válaszok erre a hozzászólásra

  Privát üzenet küldése

  

  S_x96x_S

  addikt

  érdekesség a CPU cache témához - IBM-es L4 cache topologia ..

  Did IBM Just Preview The Future of Caches? ( AnandTech )

  "That means a single IBM z15 system was 25 x 696mm2 of silicon, 20 x 256 MB of L3 cache between them, but also 5 x 960 MB of L4 cache, connected in an all-to-all topology."

  ian Cutress a cikk irója -nagyon ráizgult:

  "How Is This Possible? Magic."
  ...
  "It makes me think what might be relevant and possible in x86 land, or even with consumer devices.
  I’d be remiss in talking caches if I didn’t mention AMD’s upcoming V-cache technology, which is set to enable 96 MB of L3 cache per chiplet rather than 32 MB by adding a vertically stacked 64 MB L3 chiplet on top. But what would it mean to performance if that chiplet wasn’t L3, but considered an extra 8 MB of L2 per core instead, with the ability to accept virtual L3 cache lines?
  Ultimately I spoke with some industry peers about IBM’s virtual caching idea, with comments ranging from ‘it shouldn’t work well’ to ‘it’s complex’ and ‘if they can do it as stated, that’s kinda cool’"

Új hozzászólás Aktív témák