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• #7616 S_x96x_S addikt

  Új Válasz 2022-08-28 14:01:22 #7616

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  S_x96x_S

  addikt

  piac/trendek:

  "Tachyum’s Revised Prodigy Architecture"
  https://chipsandcheese.com/2022/08/26/tachyums-revised-prodigy-architecture/

  hosszú és alapos irás ( amolyan régi Anandtech-es minőség)
  - Ian Cuttress az egyik szerzője
  - folyamatosan hasonlítják az alternativákkal és természetesen
  a ZEN is sokszor meg van említve mint összehasonlítási alap

  
  néhány kulcsszó:
  mispredict penalty / Emulation / Cache Subsystem / Frontend and Branch Prediction

  Árdekes fúziós chip - a GPU éc a CPU kombinálására,
  de a piacon nem lesz könnyű startja ....

  "Technology trends often go in cycles. Decades ago, servers, client systems, and supercomputers slowly converged to use similar hardware. For example, in the late 2000s, AMD’s hex-core K10 die saw service in client systems as the Phenom X6, and in servers and supercomputers as the Opteron 2435. But over the last decade, the trend has been slowly reversing. Supercomputers often employ GPU acceleration to increase throughput, and there’s increasing divergence between GPU architectures targeting HPC and those targeting client platforms. Ampere and Amazon have made specialized server chips optimized for cloud computing. Intel and AMD are still using the same architectures across all three categories, but even they are customizing chips to suit different markets. For example, Skylake in server form gets extra L2 and vector units tacked onto the core, and uses a mesh interconnect. AMD is planning to release Zen 4 in a second form, named Zen 4c, which trades cache capacity for core count and should better suit cloud computing."
  
  "Tachyum’s Prodigy represents a brave attempt to buck this trend. It combines a GPU’s vector throughput with a CPU’s per-thread performance, at the cost of high power consumption. However, we are still skeptical of how Tachyum can achieve all this with all the hurdles ahead of them. We did ask Tachyum about how they are achieving their CPU in 500mm2 and while we can’t disclose what they told us, we are still very skeptical of them achieving this on N5 due to not only having massive vector units but also having a large amount of analog circuits due to the large amount of DDR5 and PCIe 5 PHYs on the die."

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