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• #49 Kansas addikt paprobert #47

  Új Válasz 2021-03-08 13:46:56 #49

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  Kansas

  addikt

  válasz paprobert #47 üzenetére

  Tessék, egy elemzés, ami leírja, hogy mi volt a gond.
  "
  - The power saving features are reducing the clock frequency most of the time. This often gives low and inconsistent results in benchmark tests because the clock frequency is varying.

  - Some operating systems are not aware that the chip shares certain resources between the two cores that make up a compute unit. The consequence is that the operating system may put two threads into one compute unit while another unit is idle, or it may put two threads with different priority into the same compute unit so that a low priority thread can steal resources from a high priority thread. I don't understand why there is no CPUID function for telling which resources are shared between CPU cores. The current solution where the operating system must know the details of every CPU on the market is not practical, and it does not work with virtual CPUs etc.

  - The shared instruction fetch unit can fetch up to 32 bytes per clock cycle or 16 bytes per core. This may be a bottleneck when both cores are active and when frequent jumps produce bubbles in the pipeline.

  - The decode unit can handle four instructions per clock cycle. It is alternating between the two threads so that each thread gets two instructions per clock cycle on average. This is a serious bottleneck because the rest of the pipeline can handle up to four instructions per clock.

  - Cache bank conflicts in the data cache are so frequent that it seriously degrades the performance in some tests.

  - The code cache has only two ways which may be insufficient to service two simultaneous threads.

  - The long pipeline causes long branch misprediction penalties.

  - The pipelines can handle four instructions per clock cycle, but there are only two integer ALUs where previous processors had three. This means that two of the four pipeline lanes will be idle most of the time in integer code.

  - Some floating point operations, such as shuffle, blend and booleans, are executed in the integer vector units. This causes an extra transport delay between the floating point vector unit and the integer vector unit."

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